1. Field of the Invention
The invention relates to a method for refreshing memory cells in a dynamic memory, which memory cells are used for storing information, wherein the refreshing is conducted in order to maintain the information in the memory cells, the information stored in the memory cells at a given time is divided into information to be maintained and information not requiring maintenance, wherein at least some of such memory cells which contain information not requiring maintenance, remain unrefreshed, in which method application programs are executed. The invention also relates to an electronic device which comprises a dynamic memory containing memory cells for storing information, means for refreshing the memory cells, means for executing application programs, means for allocating a memory area from the dynamic memory for each application program for the duration of its execution, and means for deallocating said memory area after the execution of the application program.
2. Brief Description of Related Developments
Especially for temporary storage of data, random access memories (RAM), such as static random access memories (SRAM) and dynamic random access memories (DRAM), are used e.g. for the reason that they enable relatively fast reading and writing of data when compared with other rewritable memory types, such as the non-volatile random access memory (NVRAM).
In memory cells of static memories, the data written therein is maintained when a voltage is coupled to the memory, but in dynamic memories, the data written in the memory cells must be refreshed at regular intervals in order to maintain the data. In static memories, the memory cell is typically formed of several CMOS transistors, or the like. In dynamic memories, the memory cell typically comprises one CMOS transistor and a capacitor. Thus, the memory cell of a dynamic memory requires a smaller surface area and is less expensive than the memory cell of a static memory. Therefore, dynamic memories are used especially in applications requiring a large memory capacity. In the memory cells of the dynamic memory, a charge stored in the capacitance gradually fades away e.g. due to leakage currents. Thus, the memories have to be provided with means for maintaining (refreshing) the data (charge) stored in the memory cells at intervals. This increases the power consumption of the electronic device when compared with a situation where static memories are used as random access memories.
Especially in portable electronic devices, the aim is to minimize this power consumption in order to prolong the operating time of the device. The power consumption of the memory has not, however, been a significant drawback, because the memory quantity has been relatively small and a large share of the power consumption has been caused by other functions of the electronic device.
Lately, however, the features of portable electronic devices, such as communication devices have been developed, and the quantity of random access memory has been significantly increased. This is because e.g. the applications used in such portable electronic devices require more efficiency and memory capacity than before. The use of the static memory in such applications is restricted by the relatively high price of the static memory. Another restricting factor for the use of the static memory is the large size it requires, wherein the size of the device should be increased in order to implement the necessary memory capacity in the electronic device. However, the aim is to further reduce the size of portable electronic devices, and thus to use the dynamic memory as a random access memory.
There are primarily two types of dynamic memories, an asynchronous dynamic memory (DRAM) and a synchronous dynamic memory (SDRAM). Furthermore, there may be differences in the internal structures of memories of the same basic type, for example as regards the organization of the memory cells, cache memory, and a possible division into blocks (bank). The difference between asynchronous and synchronous memories lies primarily in the fact that in synchronous DRAM memories, data is written in bursts and in a synchronous manner controlled by a clock signal. In asynchronous and synchronous DRAM memories, the memory cells are organized in a matrix format, wherein the memory is provided with a control logic by means of which it is possible to indicate each memory cell of the matrix. The control logic comprises means for indicating a matrix row and means for indicating a matrix column. The address is typically transmitted in two phases in such a way that in the first phase a matrix row address corresponding to the target address is written in the memory and in the second phase a matrix column address is written in the memory. From these row and column addresses, the control logic of the memory produces a signal to indicate the correct memory cell in the matrix. Typically, these different row and column addresses are written on the same address lines with the difference that when writing the row address, the memory is informed of the row address in question by means of a separate row address strobe line (RAS), and correspondingly, when writing the column address, the memory is informed of the column address in question by means of a separate column address strobe line (CAS).
In an electronic device, the width of the data bus typically equals the width of a byte (8 bits), or its multiple (16, 32 bits). This can be implemented either in such a way that each bit is provided with one or more dynamic memory circuits (parallel coupling of the memory circuits), or that dynamic memory circuits are used which contain several memory matrices integrated therein, for example 8 matrices in parallel. These dynamic memories can also be implemented in such a way that they are integrated in connection with so-called ASIC circuits as is known by anyone skilled in the art.
In dynamic memory circuits of prior art, the refreshing of the memory is arranged in such a way that a memory refresh logic refreshes the memory at intervals, advantageously in such a way that the memory refresh logic indicates each matrix row at a time, reads the information content of this matrix row into an intermediate buffer and writes it back into this matrix row. The refresh logic goes through each matrix row and performs the aforementioned refresh procedures. The refreshing can be conducted either in a continuous manner or between other read/write operations, in such a way, however, that the maximum refresh sequence allowed is not exceeded in any memory cell of the matrix.
There are also known dynamic memories which are provided with a so-called self refresh function, wherein an external memory refresh controller initiates a self refresh function for the dynamic memory. Thus, an internal timer of the memory updates a refresh counter which is used to maintain information on the memory area (memory row) to be refreshed at a time. With respect to retaining data, it is important to refresh each memory cell sufficiently often in the self refresh function as well.
Especially for portable electronic devices, different functions for attaining savings in power consumption have been developed to obtain a longer operating time for the electronic device. There can be several such power down modes, and the savings in the power consumption attained thereby can vary. Such power down modes include for instance an idle state and a standby state. In these different power down modes, only some of the functions of the electronic device are active. For example the micro processing unit (MPU) of the electronic device does not execute a program code but waits for an activation strobe from the timer. In the power down mode it is, however, necessary to refresh the dynamic memories. If the memory refresh is implemented with a controller separate from the memories, this memory controller has to function also in the different power down modes. If memories including a refresh logic are used as a dynamic memory, the refresh logic has to function also in the different power down modes. Thus, the refresh functions of the dynamic memories form a major part of the power consumption in these power down modes. This problem becomes even worse, because the need for fast random access memory is increased in new electronic devices. Some dynamic memories have the possibility of setting the memory into a power down mode but the maximum duration of this power down mode at a time is restricted to the length of the refresh sequence, after which the memory has to be reset into a normal mode for the duration of the refreshing.